HOWARD J. COHEN, Ph.D.
President
Cohen Software Consulting, Inc.
3272 Cowper Street
Palo Alto, CA 94306-3004
(650) 856-8123
(650) 856-4273 (fax)
howard@cohensw.com
http://www.cohensw.com

Selected Projects

• Staff Engineer, Quickturn Design Systems, Mountain View, CA
   
  • Group leader for parsers group, responsible for all Enterprise, Mars, and Quest product netlist parsers (Verilog, TEGAS and variants, EDIF, BDLS, etc.).
     
  • Trouble shooting, performance enhancement and bug fixing for the Enterprise product's netlist database and the several parsers that feed it. Likewise for the Mars and Quest software products.
     
  • Design and implementation of a Verilog front-end for the Quest product, including X11/Motif GUI (using TeleUse), using an object-oriented database (Objectivity) and an Oryx grammar front-end. Managed relationship with third-party supplier of front-end tools used in the Verilog import program.
     
  • Design and implementation of an incremental import capability (ECO) using a common software layer for all import programs.
     
  • Languages used were ANSI C and C++ on SPARC-10's; tools include Purify, Quantify and ObjectCenter. Code was also ported to Solaris and to RS6000's and HP9000's.
  
  
• Project Lead, ViP RunTime Group, Zycad Corporation, Fremont, CA

  Project leader of a group of 5 engineers writing the run-time support software for a hardware VHDL behavioral simulator. This included design partitioning among multiple processors per board and multiple boards per simulator, symbol table creation and manipulation, downloading of the simulation code and the run-time kernel to the target hardware, text and file i/o support, and support for debugging (breakpoints, trace, browsing). Responsible for the Browser subsystem. Work involved coordination with the compiler and hardware groups at Zycad, as well as with our partner companies (including Synopsis, Cadence, Dazix, Vantage, and others) who provide the simulation front end to ViP software. ViP (VHDL Instruction Processor) was a new product, introduced at DAC 92. Development environment was Sun Sparcs, Unix, ANSI C (gcc), as well as Mips for embedded code. Host side software was also to be ported to RS6000, HP/Apollo, and other engineering workstations.
  

• LSI Logic, Milpitas, CA

  Designed and implemented a clock tree analysis program which parsed several ASCII layout and technology files, calculated time delays and skews for multi-level clock trees using an RC-tree approximation, reported statistics at all levels of the tree, and created Spice decks for the four extremal nets as well as any single net the user might select. Environment was Sun Sparc, Unix, and C.
  

• Engineering Data Xpress, San Jose, CA

  Designed and implemented a CAD Framework Initiative (CFI) procedural interface to the EDI database (which is based on EDIF, the Electronic Design Interchange Format). Extended the functionality of the EDI procedural interface to support this project, including implementing a schematic to net list translator. Computers used were 386-based PC's under DOS, and an Apollo DN3000 under AEGIS; language was C.
  

• Senior Software Engineer and Group Leader, DAISY Systems Corporation, Mountain View, CA
   
  • Algorithm design, implementation, and documentation for the Gatemaster project. This involved providing software (and graphical) tools for the LSI and VLSI design engineer to go from the schematic to actual component layout and interpin routing on gate arrays.
     
  • Designed a text syntax for presenting gate array connectivity and layout information from the Gatemaster data base to chip manufacturers, helped negotiate its acceptance by a major semiconductor company, and implemented the program (MAKE) which interrogates the data base and produces the file. Also worked on intercomputer communications protocols for the data transfer process and debugging the entire system from front to back.
     
  • Created and implemented a tool which increased the success rate of the automatic routers for gate array net interconnections. This tool not only significantly increased the number and fraction of nets routable to completion but also immediately indicated unroutable chips before any time was spent trying to route them, thus saving the design engineer many hours of wasted labor.
     
  • Worked on an automatic/interactive placement tool for gate array layout based on a force relaxation model for constructive initial placement. Adapted it from some models in the literature, designed its interface with the user and with the Gatemaster data base, its internal data structures, and the details of its implementation.
     
  • Project leader, designer, and implementor of a placement improvement system for gate arrays based on component interchange algorithms with user-selectable metrics and component selection criteria.
     
  • Project leader of a group of senior and junior level system analysts addressing the issues of placement on gate arrays (CAD/CAE), providing technical supervision, coordination, and training. Informally worked with junior (and new) programmers, doing some technical training and supervision.
     
  • Group Leader of a group of several senior level system analysts addressing the issues of hardware acceleration of semi-custom chip component placement algorithms, including design and implementation of computationally intensive advanced algorithms (such as simulated annealing) to be implemented in microcode, systems embedding, and a user friendly high level interface to the design engineer.
     
  • Work in the interactive editor group for a high-level correct-by-construction editor for full custom VLSI chip planning and layout.
     
  • Member of a team designing and implementing a layout verification package for full-custom VLSI chips to be integrated with the Chipmaster. Package included electrical rules checking, device and net recognition, layout versus schematic checks, layout parameter extraction, interface to schematic capture systems, SPICE simulator, and digital system simulators; user interface, data structures and algorithms.
     
  • Computers used were the Intel Microprocessor Development System for the 8086, and the DAISY Logician (an 8086, 80286, or 80386 based engineering workstation) with MAESTRO and DAISY-DNIX operating systems; languages used were PL/M-86, C, and Metaware PASCAL.